1. Field of the Invention
The present invention relates to a multi-chip device including a plurality of chips. The present invention further relates to a method for producing a multi-chip device comprising a plurality of chips.
2. Description of the Related Art
Market requirements demand constantly increasing storage capacity of memory modules. In practice, however, the rate of increase in capacity dictated by the market is not achievable. Consequently, there is a technological gap which is nowadays filled by stacking memory chips onto each other to provide sufficient memory capacity on a memory module.
A number of stacking technologies are known. In one stacking technique, a two or more memory chips are stacked upon each other, each chip being separated by a spacer. Each of the memory chips is separately wire-bonded onto a common substrate which provides an electrical redistribution to, e.g., solder balls and the like by which the stacked chip device can be attached to the memory module board.
Furthermore, it is well known to stack a number of memory chip packages onto a package stack as, e.g., Ball Grid Array (BGA) packages and the like by providing additional contacting pads on a substrate surface of the BGA opposing the surface on which the solder balls are arranged. In this way the ball grid arrays can be soldered onto each other to produce a memory chip stack.
In another technology, memory chips may be provided with through-chip-connections which are used to provide an electrical interconnection between two contact elements on different main surfaces of the chip. The electronic circuit of one chip can be connected to the electronic circuit of an adjacent chip by adjoining the contact elements, wherein the memory chips are stacked without providing a spacer between them such that a high storage density per volume unit can be achieved.
One problem with manufacturing stacked memory chips, is that the manufacturing yield decreases substantially. This is due, at least in part, to the number of manufacturing steps between the providing of the single bare chips and the completing of the multi-chip package, each step having a certain likelihood of a failure. The decrease of the manufacturing yield is substantially independent from the stacking technology used.
Therefore, there is a need for a yield-efficient multi-chip device and a method of manufacturing the same.